1. Technical Field
This disclosure relates to semiconductor memories and more particularly, to a distributed block redundancy device and method for providing redundant circuits for semiconductor circuits.
2. Description of the Related Art
Semiconductor memory chips, for example dynamic random access memory chips (DRAM), are typically provided with redundant row/column lines to provide backup circuits in situations where a row/column line fails or is working improperly. The redundant row/column or redundancy is used to access sense amplifiers and therefore memory cells that would have otherwise been lost due to the defective row/column line.
Conventional redundancy schemes for memory circuits may be categorized into two types. These are a distributed redundancy approach and a block redundancy approach. The distributed redundancy approach is typically more area efficient, but less flexible. The block redundancy has a larger area impact and more flexibility.
Referring to FIG. 1, an illustrative memory device 10 is shown for implementing block redundancy. A 16 megabit (M) memory block or bank 12 includes 16, 1 M blocks 14. Each block 14 includes 512 wordlines WL. A faulty wordline, that is any of the 8,192 (512.times.16) or so wordlines, may be replaced by a redundant wordline RWL in a redundancy block 20. In this example, 40 wordline replacements are possible for a 16 M memory. The 40 wordline replacements in redundancy block 20 include logical replacements in regions 21 where one logical element corresponds to one physical wordline. This approach permits replacement of any faulty wordline of block 12 making this approach very flexible. The flexibility is provided by using a block redundancy, however the block redundancy requires its own sense amplifier 23. The sense amplifier 23 requires a relatively large area, and this is particularly noticeable in memory devices having a large number of banks since each bank requires its own redundant block.
Referring to FIG. 2, an illustrative memory device 30 is shown for implementing distributed redundancy. In a distributed redundancy approach, redundant elements are evenly distributed over a large number of relatively small sub-units. In this example, each 1 M unit 32 has 8 spare wordlines which can replace any failing wordline within the 1 M unit. One logical element corresponds to 1 physical wordline. Sense amplifiers are disposed in regions 33.
Although the repair domain can be increased, a problem may arise if multiple wordlines are activated. FIG. 2 additionally illustrates a repair over a 4 M domain as indicated. Since a neighboring 1 M unit 32' to the 4 M region has an active wordline 34, sense amplifier contention may occur in sense amplifier 33a because a wordline has to be sensed at both sides of the sense amplifier which is generally not possible. To avoid this situation the maximum repair region is reduced to 2 M. In designs with a large number of bits per bitline and numerous memory banks, the distributed redundancy approach often results in sense amplifier sharing problems.
Therefore, a need exists for a redundancy scheme requiring less area and having a larger repair domain. A further need exists for a replacement scheme that does not result in sense amplifier contention.